References
[1]. Mo, F., Spano, C. E., Ardesi, Y., Ruo Roch, M., Piccinini, G., and Vacca, M. (2023) Ns-gaafet compact modeling: technological challenges in sub-3-nm circuit performance. Electronics Newsweekly.
[2]. Kumar, V., Maurya, R. K., Rawat, G., Debnath, R. G., and Mummaneni, K. (2024) Noise analysis of nc-gaafet cylindrical nanowire with non-uniform interface trap charge. IOP Publishing Ltd.
[3]. Zhuo, Y., Li, X. L., Sun, Y. B., Li, X. J., and Guo, A. (2018) Statistical Variability Analysis in Vertically Stacked Gate All Around FETs at 7 nm Technology. (2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)). IEEE.
[4]. Gao, Y. (2020) Research of Process Variations of Gate All Around Field Effect Transistor (GAAFET) and Its Impact on Performance of SRAM, Doctoral dissertation, East China Normal University.
[5]. Tang, J., Jiang, J., Gao, X., Gao, X., and Peng, H. (2025) Low-power 2d gate-all-around logics via epitaxial monolithic 3d integration. (Nature Materials), 1-8.
[6]. Pott, V., Moselund, K. E, Bouvet, D., De Michielis, L., and Ionescu, A. M. (2008) Fabrication and characterization of gate-all-around silicon nanowires on bulk silicon. IEEE Transactions on Nanotechnology, 7(6), 733-744.
[7]. Lee, J.K., Woo, C., Kim, J., Kang, M., Jeon, J., and Shin, H. (2019) Analysis of variation and ferroelectric layer thickness on negative capacitance nanowire field-effect transistor. Journal of nanoscience and nanotechnology, 19(10), 6710.
[8]. Huang, Y. C., Chiang, M. H., Wang, S. J., and Fossum, J. G. (2017) Gaafet versus pragmatic finfet at the 5nm Si-based CMOS technology node.(IEEE Journal of the Electron Devices Society) [5](3), 164-169.
[9]. Hemantha, G. R., Priya, A. S., Suman, J. V., Rao, T. V. J., Priyadarshini, G. M. A., and Mallam, M. (2024) Characterization and Modeling of Gate-All-Around FET (GAA FET) for Low-Power and High-Performance Applications. (2024 International Conference on Advances in Modern Age Technologies for Health and Engineering Science (AMATHE)). IEEE
[10]. Singh, S., and Raman, A. (2018). A dopingless gate-all-around (gaa) gate-stacked nanowire fet with reduced parametric fluctuation effects. Journal of Computational Electronic.
[11]. Chen, Z., Shan, H., Ding, Z., Wu, X., Cen, X., and Ma, X., et al. Surface-potential-based drain current model of gate-all-around tunneling fets. IEEE Journal of the Electron Devices Society, 12.