Fundamental Structure and Key Performance Applications of Nanoelectronics Device GAAFET
Research Article
Open Access
CC BY

Fundamental Structure and Key Performance Applications of Nanoelectronics Device GAAFET

Zijie Ma 1*
1 Xi’an Jiaotong -Liverpool University
*Corresponding author: Zijie.Ma24@student.xjtlu.edu.cn
Published on 2 October 2025
Journal Cover
ACE Vol.188
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-80590-397-0
ISBN (Online): 978-1-80590-398-7
Download Cover

Abstract

With the development of integrated circuit technology to 3 nm and below advanced nodes, traditional transistors are difficult to meet the requirements of high performance and low power consumption due to the short channel effect and insufficient electrostatic control ability. The gate-all-around field-effect transistor (GAAFET) has emerged as the core candidate of next-generation nanoelectronics devices under its unique structure. However, its complex structure brings many research problems, such as the traditional physical model is difficult to accurately describe the electrical characteristics, and the efficiency of parameter extraction is low. As semiconductor technology continues to move towards more advanced nodes, GAAFET is expected to become the core support to break through the limits of Moore's Law. In the future, we can focus on complex application scenarios, further strengthen the research on the performance stability and reliability of GAAFET, overcome the problems of precise control of multi-layer stack thermal coupling and noise suppression at different frequencies, and accelerate its industrialization from laboratory theoretical exploration. At the same time, we will actively expand the integration path with emerging technologies such as quantum computing assistant circuits and brain-like chips, tap more potential application scenarios such as ultra-low power Internet of Things devices and high-performance edge computation chips, help 5G/6G communications, artificial intelligence, and other frontier industries achieve leapfrog development, and open up a new technology track and growth space for the semiconductor industry.

Keywords:

Gate-All-Around Field-Effect Transistor (GAAFET), nanoelectronics, integrated circuits, semiconductor

View PDF
Ma,Z. (2025). Fundamental Structure and Key Performance Applications of Nanoelectronics Device GAAFET. Applied and Computational Engineering,188,31-38.

References

[1]. Mo, F., Spano, C. E., Ardesi, Y., Ruo Roch, M., Piccinini, G., and Vacca, M. (2023) Ns-gaafet compact modeling: technological challenges in sub-3-nm circuit performance. Electronics Newsweekly.

[2]. Kumar, V., Maurya, R. K., Rawat, G., Debnath, R. G., and Mummaneni, K. (2024) Noise analysis of nc-gaafet cylindrical nanowire with non-uniform interface trap charge. IOP Publishing Ltd.

[3]. Zhuo, Y., Li, X. L., Sun, Y. B., Li, X. J., and Guo, A. (2018) Statistical Variability Analysis in Vertically Stacked Gate All Around FETs at 7 nm Technology. (2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)). IEEE.

[4]. Gao, Y. (2020) Research of Process Variations of Gate All Around Field Effect Transistor (GAAFET) and Its Impact on Performance of SRAM, Doctoral dissertation, East China Normal University.

[5]. Tang, J., Jiang, J., Gao, X., Gao, X., and Peng, H. (2025) Low-power 2d gate-all-around logics via epitaxial monolithic 3d integration. (Nature Materials), 1-8.

[6]. Pott, V., Moselund, K. E, Bouvet, D., De Michielis, L., and Ionescu, A. M. (2008) Fabrication and characterization of gate-all-around silicon nanowires on bulk silicon. IEEE Transactions on Nanotechnology, 7(6), 733-744.

[7]. Lee, J.K., Woo, C., Kim, J., Kang, M., Jeon, J., and Shin, H. (2019) Analysis of variation and ferroelectric layer thickness on negative capacitance nanowire field-effect transistor. Journal of nanoscience and nanotechnology, 19(10), 6710.

[8]. Huang, Y. C., Chiang, M. H., Wang, S. J., and Fossum, J. G. (2017) Gaafet versus pragmatic finfet at the 5nm Si-based CMOS technology node.(IEEE Journal of the Electron Devices Society) [5](3), 164-169.

[9]. Hemantha, G. R., Priya, A. S., Suman, J. V., Rao, T. V. J., Priyadarshini, G. M. A., and Mallam, M. (2024) Characterization and Modeling of Gate-All-Around FET (GAA FET) for Low-Power and High-Performance Applications. (2024 International Conference on Advances in Modern Age Technologies for Health and Engineering Science (AMATHE)). IEEE

[10]. Singh, S., and Raman, A. (2018). A dopingless gate-all-around (gaa) gate-stacked nanowire fet with reduced parametric fluctuation effects. Journal of Computational Electronic.

[11]. Chen, Z., Shan, H., Ding, Z., Wu, X., Cen, X., and Ma, X., et al. Surface-potential-based drain current model of gate-all-around tunneling fets. IEEE Journal of the Electron Devices Society, 12.

Cite this article

Ma,Z. (2025). Fundamental Structure and Key Performance Applications of Nanoelectronics Device GAAFET. Applied and Computational Engineering,188,31-38.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

About volume

Volume title: Proceedings of CONF-MCEE 2026 Symposium: Advances in Sustainable Aviation and Aerospace Vehicle Automation

ISBN: 978-1-80590-397-0(Print) / 978-1-80590-398-7(Online)
Editor: Ömer Burak İSTANBULLU
Conference date: 14 November 2025
Series: Applied and Computational Engineering
Volume number: Vol.188
ISSN: 2755-2721(Print) / 2755-273X(Online)