The Review of Structure Development of Gate-stacked Double-Gate MOSFETs
Research Article
Open Access
CC BY

The Review of Structure Development of Gate-stacked Double-Gate MOSFETs

Wanchen Wang 1*
1 Xiamen University
*Corresponding author: 37520242204675@stu.xmu.edu.cn
Published on 23 October 2025
Journal Cover
TNS Vol.145
ISSN (Print): 2753-8826
ISSN (Online): 2753-8818
ISBN (Print): 978-1-80590-467-0
ISBN (Online): 978-1-80590-468-7
Download Cover

Abstract

Gate-stacked double-gate (DG) MOSFETs, featuring a thin SiO₂ interfacial layer combined with high-k dielectrics, improve electrostatics, suppress leakage, and mitigate short-channel effects, enhancing the performance implication. They are promising for low-power electronics, high-performance computing, and biosensing. Conventional MOSFET scaling faces critical bottlenecks, as high-k dielectrics alone suffer from leakage and interface issues. At the same time, structural innovations such as FinFETs cannot fully suppress short-channel effects at advanced nodes. GAA demonstrates good performance, but costs excessively. This work innovatively proposes co-optimizing materials (Al₂O₃, HfO₂, La₂O₃) and structures (strain engineering, dual-material gates, multigate topologies) in gate-stacked double-gate (DG) MOSFETs, integrating high-k stacks with multigate architectures to reinforce electrostatics and scalability. Such synergy ensures enhanced performance while meeting the dual demands of low-power electronics, high-performance computing, and emerging biosensing applications.

Keywords:

Gate-stacked double-gate MOSFETs, high-κ dielectrics, short-channel effects, low-power electronics.

View PDF
Wang,W. (2025). The Review of Structure Development of Gate-stacked Double-Gate MOSFETs. Theoretical and Natural Science,145,17-27.

References

[1]. X. Zhou, L. Yang, C. Liu, Y. Zhao, and K. Zhang, “Short-Channel Effect Suppression and Footprint Reduction in Double Gate-All-Around Field Effect Transistors and Inverters Based on Two-Dimensional Materials, ” ACS Appl. Electron. Mater., vol. 6, no. 7, pp. 3852–3861, Jul. 2024, doi: 10.1021/acsaelm.4c01319.

[2]. Y. Cui, Z. Zhong, and C. Wang, “High-k gate dielectrics for advanced MOS devices, ” Nat. Rev. Mater., vol. 6, pp. 131–148, 2021, doi: 10.1038/s41578-020-00243-4.

[3]. J. Saint-Martin, A. Bournel, and P. Dollfus, “Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation, ” arXiv preprint cond-mat/0505168, May 2005. Available: https: //arxiv.org/abs/cond-mat/0505168.

[4]. G. V. Reddy and M. J. Kumar, “A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET – Two-Dimensional Analytical Modeling and Simulation, ” arXiv, Aug. 2010.

[5]. P. K. Pradhan, S. K. Mohapatra, P. K. Sahu, and S. Parija, “Impact of Strain on Fully Depleted Strained Gate Stack Double-Gate (FD-S-GS-DG) MOSFET: A Simulation Study, ” ECTI Trans. Electr. Eng., Electron. Commun., vol. 17, no. 2, pp.--, 2024.

[6]. E. Farzana, S. Chowdhury, R. Ahmed, and M. Z. R. Khan, “Performance analysis of nanoscale double gate MOSFETs with high-k gate stack, ” Appl. Mech. Mater., vols. 110–116, pp. 1892–1899, Oct. 2011, doi: 10.4028/www.scientific.net/AMM.110-116.1892.

[7]. M. Salmani-Jelodar, H. Ilatikhameneh, S. Kim, K. Ng, and G. Klimeck, “Optimum high-k oxide for the best performance of ultra-scaled double-gate MOSFETs, ” arXiv preprint arXiv: 1502.06178, Feb. 2015. Available: https: //arxiv.org/abs/1502.06178.

[8]. S. K. Singh, R. Kumar, and P. K. Yadav, “Thermal influence on performance characteristics of double gate MOSFET biosensors with gate stack configuration, ” Discover Appl. Sci., vol. 6, no. 202, pp. 1–12, Aug. 2024, doi: 10.1007/s42452-024-06055-1.

[9]. G. Fiori and G. Iannaccone, “Ultralow-power tunnel FETs with high-k gate stacks for beyond-CMOS applications, ” IEEE Trans. Nanotechnol., vol. 10, no. 6, pp. 1409–1416, Nov. 2011, doi: 10.1109/TNANO.2011.2165073.

[10]. A. T. Shora, “3-D Modelling Based Comprehensive Analysis of High-κ Gate Stack Graded Channel Dual Material Trigate MOSFET, ” J. Semicond., vol. 39, no. 12, Art. 124016, 2018.

[11]. E. Dastjerdy, R. Ghayour, and H. Sarvari, “Simulation and Analysis of the Frequency Performance of a New Silicon Nanowire MOSFET Structure, ” Physica E: Low-Dimensional Systems and Nanostructures, vol. 45, pp. 66–71, Aug. 2012, doi: 10.1016/j.physe.2012.07.007.

[12]. H. Jung, “Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide, ” Int. J. Electr. Comput. Eng., vol. 11, no. 3, pp. 2522–2530, Jun. 2021, doi: 10.11591/ijece.v11i3.pp2522-2530.

[13]. K. Martens, A. Vandooren, S. Sioncke, and G. Groeseneken, “Performance projections for gate-stack engineered double-gate MOSFETs, ” IEEE Trans. Electron Devices, vol. 61, no. 12, pp. 4145–4152, Dec. 2014, doi: 10.1109/TED.2014.2365162.

[14]. Z. Dibi, R. Boujamaa, and A. Jarray, “New gate stack double diffusion MOSFET design to improve the electrical performances for power applications, ” Proc. World Acad. Sci. Eng. Technol., vol. 1, no. 11, pp. 617–621, 2007.

Cite this article

Wang,W. (2025). The Review of Structure Development of Gate-stacked Double-Gate MOSFETs. Theoretical and Natural Science,145,17-27.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

About volume

Volume title: Proceedings of CONF-CIAP 2026 Symposium: International Conference on Atomic Magnetometer and Applications

ISBN: 978-1-80590-467-0(Print) / 978-1-80590-468-7(Online)
Editor: Marwan Omar, Jixi Lu, Mao Ye
Conference date: 30 January 2026
Series: Theoretical and Natural Science
Volume number: Vol.145
ISSN: 2753-8818(Print) / 2753-8826(Online)